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Order Number: MC33253/D Rev 3, 03/2001
Advance Information
MC33253
55 VOLTS
SEMICONDUCTOR TECHNICAL DATA
Full Bridge Pre-Driver
The MC33253 is a full bridge driver including integrated charge pump, two independent high and low side driver channels. The high and low side drivers include a cross conduction suppression circuit, which, if enabled, prevents the external power FETs from being on at the same time. The drive outputs are capable to source and sink 1 A pulse peak current. The low side channel is referenced to ground, the high side channel is floating above ground. A linear regulator provides a maximum of 15.5V to supply the low side gate driver stages. The high side driver stages are supplied with a 10V charge pump voltage. Such built-in feature, associated to external capacitor provides a full floating high side drive. An under- and over-voltage protection prevents erratic system operation at abnormal supply voltages. Under fault, these functions force the driver stages into off state. The logic inputs are compatible with standard CMOS or LSTTL outputs. The input hysteresis makes the output switching time independent of the input transition time. The global enable logic signal can be used to disable the charge pump and all the bias circuit. The net advantage is the reduction of the quiescent supply current to under 10A. To wake up the circuit, 5 V has to be provided at G_EN. A built-in single supply operational amplifier could be used to feedback information from the output load to the external MCU. * VCC Operating Voltage Range from 5.5 V up to 55 V * VCC2 Operating Voltage Range from 5.5 V up to 28 V * Automotive Temperature Range -40C to 125C * 1A Pulse Current Output Driver * Fast PWM Capability * Built-In Charge Pump * Cross Conduction Suppression Circuit
DW SUFFIX
PLASTIC PACKAGE CASE 751F-05
PIN CONNECTIONS
(TOP VIEW) CASE 751F-05
VCC C2 CP_OUT
1 2 3
28 ISOUT 27 G_EN 26 /CCS 25 SRC_HS2 24 GATE_HS2 23 /IN_HS2 22 IN_HS2 21 /IN_LS2 20 IN_LS2 19 GATE_LS2 18 GND2 17 IS-IN 16 IS+IN 15 C1
SRC_HS1 4 GATE_HS1 5 /IN_HS1 IN_HS1 /IN_LS1 IN_LS1 6 7 8 9
GATE_LS1 10 GND1 LR_OUT VCC2 GND_A 11 12 13 14
ORDERING INFORMATION
Device PC33253DW Temperature Range -40oC to +125oC
Package
SOIC28
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc., 2001. All rights reserved.
Page 1/15
MC33253
Figure 1. Principal Building Blocks
Ccp C1 VCC UV/OV Detect VDD VCC VCC RDY EN GND G_EN VCC2 VCC2 +13.5 V VDD CP_OUT CLR_OUT LR_OUT Vgs_hs Charge Pump C1 C2 Vpos +13.5 V CCP_OUT 5.5 V... 55 V Linear +5.0 V EN Reg GND +13.5 V HIGH AND LOW SIDE CONTROL WITH CHARGE PUMP CCS Vgs_ls CCS Vgs_ls VCC IN_HS1 VDD VDD/VPOS Level Shift Input & CCS VDD LOGIC VDD/VCC Level Shift Pulse Generator Pulse Generator G_LOW_H G_LOW_LS IN Output Driver OUT GATE_HS1 SRC_HS1 /IN_HS1 VCC VCC C2 VCC2 VCC2 5.5 V... 28 V
/CCS
BRG_EN BRG_EN
IN_LS1 IN Output Driver OUT GATE_LS1
/IN_LS1
HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION
BRG_EN IN_HS2 VDD
CCS
Vgs_ls VCC VDD/VPOS Level Shift Pulse Generator G_LOW_H G_LOW_LS IN Output
Driver
OUT
GATE_HS2 SRC_HS2
/IN_HS2 Input & CCS VDD VDD/VCC Level Shift
IN_LS2
Pulse Generator
IN
Output Driver
OUT
GATE_LS2
/IN_LS2 HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION SENSE CURRENT AMPLIFIER
CAO
GND ISOUT
+
CACA+
IS+IN IS-IN rev3.0 - 2/15
MC33253
MOTOROLA
MC33253
parameters are absolute voltages referenced to GND.
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
Rating Supply Voltage1 Supply Voltage2 (NOTE 1) Linear Regulator Output Voltage High Side Floating Supply Absolute Voltage High Side Floating Source Voltage High Side Gate Voltage High Side Gate Source Voltage
Symbol VCC VCC2 VLR_out VCP_OUT VSRC_HS VGATE_HS VGATE_HS - VSRC_HS IS VCP_OUT - VGATE_HS VGATE_LS VG_EN VIN VC1 VC2 VCAO VCAVCA+ VESD
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max 65 35 18 65 65 65 20
Unit V V V V V V V
High Side Source Current from Cpout in Switch On State High Side Floating Supply Gate Voltage
250 -0.3 65
mA V
Low Side Output Voltage Wake up Voltage Logic Input Voltage Charge Pump Capacitor Voltage Charge Pump Capacitor Voltage Operational Amplifier Output Voltage Operational Amplifier Inverting Input Voltage Operational Amplifier Non Inverting Input Voltage ESD Voltage on any Pins (HBM, 100pF, 1.5kOhms) Power Dissipation and Thermal Characteristics Maximum Power Dissipation@25C Thermal Resistance Junction-to-Air Operating Junction Temperature Storage Temperature
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -2.0
17 35 10 VLR_OUT 65 7 7 7 2.0
V V V V V V V V kV
PD RJA TJ Tstg -40 -65
2 60 +150 +150
W C/W C C
OPERATING CONDITIONS Typical values for TA = 25C, Min/Max values for TA = -40C to +125C Rating Supply Voltage1 Supply Voltage2 High Side Floating Supply Absolute Voltage
NOTE1: VCC can sustain load dump pulse 40V, 400ms, 2Ohms
Symbol VCC VCC2 VCP_OUT
Min 5.5 5.5 VCC+4
Max 55 28 VCC+11but<65
Unit V V V
MC33253
MOTOROLA
rev3.0 - 3/15
MC33253
Typical values for TA = 25C, Min/Max values for TA = -40C to +125C, unless otherwise specified.
STATIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified. Characteristics LOGIC SECTION Logic "1" Input Voltage (IN_LS & IN_HS) Logic "0" Input Voltage (IN_LS & IN_HS) Logic "1" Input Current Vin=5V Logic "0" Input Current Vin=0V Logic "0" Input Voltage (/IN_LS & /IN_HS&/CCS) Logic "1" Input Voltage (/IN_LS & /IN_HS&/CCS) Logic "0" Input Current Vin=5V Logic "1" Input Current Vin=0V Wake Up Input Voltage (G_EN) Wake Up Current (G_EN) VG_EN = 14 V LINEAR REGULATOR SECTION Linear Regulator VLR_OUT @ VCC2 from 16.5 to 28 V, ILOAD from 0mA to 20mA Linear Regulator VLR_OUT @ VCC2 =12 V, ILOAD = 20mA VLR_OUT @ VCC2 =5.5V, ILOAD =TBD, VCC = 5.5V CHARGE PUMP SECTION Charge Pump Output Voltage, referenced to VCC ILOAD = 0mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC ILOAD = 7mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC2 = VCC=5.5V ILOAD = 0mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC2 = VCC=5.5V ILOAD = 7mA, CCpout=1uF Peak current through pin 15under rapid changing Vcc voltages (see Figure 6) Minimum peak voltage at pin 15under rapid changing Vcc voltages (see Figure 6) SUPPLY VOLTAGE SECTION Quiescent Vcc Supply Current VG_EN=0V Operating Vcc Supply Current (@VCC=55V and VCC2=28V) (@VCC=12V and VCC2=12V) Quiescent Vcc2 Supply Current VG_EN=0V 1 1 1 13 TBD TBD TBD TBD uA mA mA uA 3 3 3 VCP_OUT VCP_OUT VCP_OUT VLR_OUT -2 VLR_OUT -3 VLR_OUT - TBD VLR_OUT-TBD -2.0 -1.5 2.0 V V V 12 12 12 VLR_OUT VLR_OUT 13.5 VCC2 1.5 TBD 16.5 V V V 6, 8, 21, 23, 26 6, 8, 21, 23, 26 27 27 7, 9, 20, 22 7, 9, 20, 22 VIH VIL Iin+ IinVIH VIL Iin+ IinVG_EN IG_EN TBD TBD 4.5 5.0 200 200 200 2.0 2.0 10 0.8 1000 1000 10 0.8 TBD TBD VCC2 500 V V uA uA V V uA uA V uA Pin # Symbol Min Typ Max Unit
3
VCP_OUT
V
15 15
IC1 VC1min
A V
MC33253
MOTOROLA
rev3.0 - 4/15
MC33253
Characteristics Operating Vcc2 Supply Current (@VCC=55V and VCC2=28V) (@VCC=12V and VCC2=12V) Logic pin inactive (high impedance) Under Voltage Shutdown VCC2 (Note2) Under Voltage Shutdown VCC Over Voltage Shutdown VCC Over Voltage Shutdown VCC2 OUTPUT SECTION Output Sink Resistance (Turned off) VGATE_HS - VSRC_HS =1V Output Source Resistance (Turned on) VCP_OUT - VGATE_HS =0.1V High Side Source Current from Cpout in Switch On State Max Voltage (VGATE_HS - VSRC_HS), INH=1, ISmax=200mA RDS 3, 4, 5, 10, 19, 24, 25 RDS ISmax 22.0 22.0 200 18 4, 5, 24, 25 Ohms Ohms mA V Pin # 13 13 13 1 1 13 UV2 UV OV OV2 4.6 4.6 57 29.5 5.1 5.1 61 31 Symbol Min Typ Max 10 8 5.5 5.5 64 32.5 Unit mA
V V V V
4, 25
SENSE CURRENT AMPLIFIER SECTION (Internal VCC supply @ 12V) Output Dynamic Range (Isink/source = 200A) Open Loop Gain (at 25C) Input Bias Current Input Offset Voltage (at 25C) Input Common Mode Voltage Range Common Mode Rejection Ratio Sink Capability (Vo>1.1V) (Note 3) Source Capability (Vo<5V) (Note 3) Gain Bandwidth Product Operational Amplifier Output Voltage, Isink=500uA Operational Amplifier Output Voltage, Isource=500uA Operational Amplifier Slew Rate (+) Operational Amplifier Slew Rate (-) 28 28 28 28 16, 17 28 VOH VOL A IIB Vio ICMR CMRR Isink Isource GBW VCAO VCAO SR+ SR5 1 1 2.0 2.0 -5.0 0 70 3.0 3.0 1.8 0.5 2.0 4.7 5.0 300 50 1.0 5.0 5 V mV dB uA mV V dB mA mA MHz V V V/us V/us
MC33253
MOTOROLA
rev3.0 - 5/15
MC33253
DYNAMIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified. Typical values for TA = 25C, Min/Max values for TA = -40C to +125C, unless otherwise specified. Characteristics Prop. Delay HS and LS, Cload=5nF; Between 50% Input to 50% Output (see Figure 2) Turn On Rise Time, Cload=5nF ; 10% to 90% (NOTE 4) (see Figure 2) Turn Off Fall Time, Cload=5nF ; 10% to 90% (NOTE 4) (see Figure 2) Pin # 5, 6, 7, 8, 9, 20, 21, 22, 23 Symbol tPD Min Typ 200 Max 300 Unit ns
tr tf 5, 10, 19, 24
80 80
180 180
ns ns
NOTE 2: Between 4.6V and 5.5V, the device has been a non erroneous behaviour. NOTE 3: Input overdrive 1V NOTE 4: Rise time is given by time needed to charge the gate from 1V to 10V (Vice versa for fall time) NOTE : Cload corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.
N.B. In some applications a large dV/dt at Pin 2 (C2) due to sudden changes at VCC can cause a large peak currents flowing through Pin15 (C1). Positive transitions at Pin2 (C2) ;mimimum peak current : Ic1min = 2.0A tc1min = 600ns (see for peak description) Negative transitions at Pin2 (C2); maximum peak current : Ic1max = 2.0A tc1max = 600ns (see for peak description) Current sourced by Pin 15 (C1) during a large dV/dt will result in a negative voltage at Pin 15; negative transitions at Pin2(C2); minimum peak voltage: Vc1min = -1.5V tc1max = 600ns (see for peak description) Figure 2. Limits of C1 Current&Voltage with Large ValuesdV/dt of Vcc
VCC
Ic1max
tC1min
I[C1+C2]
0A
tc1max
Ic1min
V[LR_OUT]
V[C1]
0V
Vc1min
MC33253
MOTOROLA
rev3.0 - 6/15
MC33253
Figure 3. Dynamic Characteristics
/IN_HS or /IN_LS 50% 50%
50% IN_HS or IN_LS GATE_HS or GATE_LS
tpd tpd
50%
50%
tf tr
50% 10% 90% 90% 10%
Driver Characteristics Turn-On For turn-on the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: Peak Current for Rise/Fall Time (tr) and a typical PowerMosFET Gate Charge Qg. IP = Qg/tr = 75 nC/80 ns 1.0 A Turn-Off The peak current for turn-off can be obtained in the same way as for turn-on. In addition to the dynamic current, required to turn-off or turn-on the FET, various application related switching scenarios have to be considered: The output driver sources a peak current of up to 1A for 200 ns to turn on the gate. After 200 ns 100 mA are provided continuously to maintain the gate charged. The output driver sinks a peak current of up to 1A for 200 ns to turn off the gate. After 200 ns 100 mA are sinked continuously to maintain the gate discharged. In order to withstand high dV/dt spikes a low resistive path between gate and source is implemented during the off state. Figure 4. OFF-State Driver Requirement
Flyback Spike charge LS-Gate via Crss Flyback Spike pull down HSCharge Current Irss up to 2.0 A! Uncon- Drain VGS Increase Delayed Turn-Off of High Side FET trolled Turn-On of Low Side FET VBAT VBAT OFF g_hs g_hs ILOAD Ciss Crss ILOAD Ciss Crss g_hs VGATE -VDRN L1 ILOAD Ciss Crss Flyback Spike charge LS-Gate via Crss Charge Current Irss up to 2.0 A! Delayed Turn-Off of Low Side FET VBAT OFF g_hs ILOAD Flyback Spike pull down HSDrain VGS Increase Uncontrolled Turn-On of High Side FET VBAT
Crss
Crss
Crss
Crss
Ciss Irss VGATE g_ls OFF Ciss Crss
L1
L1
L1
g_ls OFF Ciss
g_ls
g_ls
Ciss
Ciss
Driver Requirement: Low Driver Requirement: Low Resistive Driver Requirement: Driver Requirement: Low Resistive Resistive Gate-Source Gate Source Path during OFF-State. High Peak Sink Current Capab. Gate-Source Path during OFF-State Path during OFF-State High Peak Sink Current Capab.
MC33253
MOTOROLA
rev3.0 - 7/15
MC33253
Driver Supply The High Side Driver is supplied from the internal charge pump buffered at CP_OUT. The low-drop regulator provides approx. 3.5 mA (fPWM = 50kHz) per gate. In case of the full bridge that means approximately. 14 mA; 7.0 mA for the high side and 7.0 mA for the low side. (Note: The average current required to switch a gate with a frequency of 100kHz is: Average Current (Charge Pump) for PWM Frq. (fPWM) and ICP = Qg*fPWM = 75 nC*100 kHz = 7.5mA. A full bridge application switch only one high side and one low side at the same time.) External capacitors on Charge Pump and on Linear Regulator are necessary to supply high peak current absorbed during switching. The Low Side Driver is supplied from built in low drop regulator. Gate Protection The low side gate is protected by the internal linear regulator, which guarantees that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump the voltage at POS_HS can be up to 65V. The high side gate is clamped internally, in order to avoid a VGS exceeding 14V. The Gate protection does not include a Flyback Voltage Clamp that protects the driver and the external FET from a Flyback voltage that can appear when driving inductive load.This Flyback voltage can reach high negative voltage values and needs to be clamped externally. Figure 5. Gate Protection and Flyback Voltage Clamp
Vgs_ls Vgs_hs M1 IN Output OUT Driver G_LOW GATE_HS VGS < 14 V SRC_HS Dcl G_LOW IN Output Driver OUT GATE_LS M2 L1 under all conditions Inductive Flyback Voltage Clamp VCC
TMOS Failure Protection All output driver stages are protected against TMOS failure conditions. If one of the external power FETs is destroyed (Gate = VCC, or Gate = Gnd) the function of the remaining output driver stages is not affected. All output drivers are short circuit protected against short circuits to ground. Cross Conduction Suppression The purpose of the cross conduction suppression is to avoid that high and low side FET are turned on at the same time, which prevents the half bridge power FETs of a shoot-through condition. The CCS can be disabled / enabled by an external signal (/CCS). - /CCS=0, the cross conduction is not allowed. - /CCS=1, the cross conduction is allowed.
MC33253
MOTOROLA
rev3.0 - 8/15
MC33253
Figure 6. Input Logic and Cross Conduction Suppression
G_EN AND AND UV_OV RDY /CCS CCS BRG_EN IN_HS 10 k AND 10 k /IN_HS AND AND OR en1_ls AND drv_ls /IN_LS en2_ls AND en1_hs OR en2_hs G_LOW_H "1" FET is Turned-Off G_LOW_LS "1" FET is Turned-Off OUT_LS "1" Turn-On FET "1" Cross Conduction Suppression is Disabled en2hs = "1", en2ls = "1" en1hs = "0", en1ls = "0" AND OUT_HS "1" Turn-On FET
EN_CP/LDO "1" Enable Charge Pump and LDO
{"1" Supply is ok
"1" Charge Pump is Ready "0" Cross Conduction Suppression is Enabled en2hs = G_LOW_LS, en2ls = G_LOW_HS
IN_LS
10 k
Logic Inputs Logic Input Voltage Range: Absolute Max : -0.3 V ... 10 V Wake Up Function: (G_EN) 4.5 V ... VCC2 During Wake-Up the logic is supplied from the G_EN pin. Low Drop Linear Regulator The low drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT and the +13.5 V for the charge pump, which generates the Vgs_hs. The low drop linear regulator provides 3.5 mA average current per driver stage. If typically VCC2 exceeds 14.5V the output is limited to 14V. Charge Pump The charge pump generates the high side driver supply voltage ( Vgs_hs), buffered at CCP_OUT. The basic circuit (Fig 7), shows charge pump without load: Figure 7. Charge Pump Basic Circuit (2)
VLR_OUT Ccp A D2 Ccp_out VCP_OUT D1
Osc.
(1)
Vbat
When the oscillator is in low state (1), Ccp is charged through D2 until its voltage reaches Vbat-Vd2. When the oscillator is in high state (2), Ccp is discharged though D1 in Ccp_out, and final voltage of the charge pump, Vcp_out is Vbat+VLR_OUT - 2Vd. The frequency of the MC33253 oscillator is about 330 kHz.
MC33253
MOTOROLA
rev3.0 - 9/15
MC33253
The Figure 8 represents a simplified circuitry of the high side gate driver. Figure 8. High Side Gate Driver
VLR-OUT Tosc2 Ccp CP_out D1 C2 D2 Tosc1
Ccp_out
C1
(3)
Vcc
T1 GATE_HS Rg HS MOSFET
T2
SRC_HS
M
LS MOSFET
pins
The transistors Tosc1 and Tosc2 are the oscillator switching MOSFETs. When Tosc1 is on, the oscillator is at low level. When Tosc2 is on, the oscillator is at high level. The high side MOSFET predriver is composed of two transistors T1 and T2. When T1 is on the HS MOSFET is turn on, when T2 is on the HS MOSFET is off. The capacitor Ccp_out provides peak current to the HS MOSFET through T1 during turn on (3) as shown in figure 11. Ccp Ccp choice depends on Power MOSFET characteristics and the working switching frequency. The following diagrams show the influence of Ccp value on Vcp_out average voltage level. The diagrams are given at two different frequencies for two power MOSFETs (MTP60N06HD and MPT36N06V). Figure 9. Vcp_out Versus Ccp
21 20.5 Vcp_out (v) 20 19.5 19 18.5 18 5 25 45 65 85
21.5
20KhZ 100 KhZ
21 20.5 Vcp_out (V) 20 19.5 19 18.5 5
20kHz 100kHz
25
45 Ccp (nF)
65
85
Ccp (nF)
MTP60N06HD (Qg=50nC) Figure 10.
MTP36N06V (Qg=40nC)
MC33253
MOTOROLA
rev3.0 - 10/15
MC33253
The smaller Ccp value is, the smaller Vcp_out value is. Moreover, for a same Ccp value, when the switching frequency increases, the average Vcp_out level decreases. For most of the applications a typical value of 33nF is recommended.
Ccp_out As shown in figure 11, at high side MOSFET turn on, Vcp_out voltage decreases. This decrease can be calculated according to Ccp_out value as following :
VCcp _ out =
Qg : Power MosFET Gate Charge
Qg Ccp _ out
The following figure is the simplified Ccp_out current and voltage waveforms. fpwm : working switching frequency Figure 11. Simplified Ccp_out Current and Voltage Waveforms
Oscillator in high state Oscillator in low state High Side turn on
V Cp_out average V Cp_out
VCcp _ out
I Cp_out
f=330kHz
fPWM
Peak Current
CLR_OUT CLR_OUT provides peak current needed by the low side MOSFET turn on. VLR_OUT decreasing is as follow:
VLR _ out =
Qg C LR _ out
Capacitors typical values In most working cases the following typical values are advised for a good charge pump performing: Ccp=33nF, Ccp_out=470nF and CLR_OUT=470nF. These values give a typical 100mV voltage ripple on Vcp_out and VLR_OUT with Qg=50nC. OP-Amp The built-in A.O.P. available in the MC33253 allows to get a voltage image of the H-bridge current. This voltage can be provided by a shunt resistor, as shown in figure 13. Typically shunt resistivity is dimensioned as low as possible (25mOhm/10A). The maximum A.O.P output voltage is 5V. Therefore a gain of 10 sets the maximum drop voltage on the sensing resistance at 500mV.
MC33253
MOTOROLA
rev3.0 - 11/15
MC33253
A differential mode is advised as shown in fig 12: Figure 12. : Differential A.O.P
R3 R4 V2 R1 V1
IS+IN
+ _ A OP
ISOUT
IS-IN R2
Vout
with R2=R4 and R1=R3,
Vout =
R2 (V 2 - V 1) R1
A gain of 10 gives
R2 = 10 ( a ) R1
To minimize the perturbations, impedance seen by the A.O.P inputs may be as low as possible. Knowing the maximum output current (2mA), the minimum value of (R1+R2) can be deduced when VOUT maximum is 5V:
( R1 + R2 ) min =
5V = 2,5k ( b ) 2mA
with (a) and (b), the minimum values of R1, R2, R3 and R4 can be calculated. R1=R3=227 Ohms and R2=R4=2.27 kOhms Over/Under Voltage Shutdown The under voltage protection becomes active at VCC below 5.5 V and the overvoltage protection is activated at VCC above 55 V or at VCC2 above 28 V. If the O/UV protection is activated the outputs are driven low, in order to switch off the FETs. Protection A protection against double battery and load dump spikes up to 55 V is given by VCC = 55 V. A protection against reverse polarity is given by the external power FET with the free wheeling diodes, forming a conducting pass from ground to VCC. An additional protection is not provided within the circuit. There is a temperature shut down protection per each half bridge. It protects the circuitry against temperature damage by blocking the output drives.
MC33253
MOTOROLA
rev3.0 - 12/15
MC33253
Figure 13. DC Motor Control with Microcontroller
VBAT VLOGIC VCC/VCC2 /G_EN /CCS C1 CAN PWM1 PWM2 PWM3 PWM4 mC CCp 33nF HS_1 LS_1 HS_2 LS_2 CURRENT FDB C2 IN_HS1 IN_LS1 IN_HS2 IN_LS2 ISOUT
CLRout 470nF LR_OUT CP_OUT 470nF CPout GATE_HS1 SRC_HS1 FULL BRIDGE DRIVER GATE_LS1 GATE_HS2 SRC_HS2 GATE_LS2 GND IS+IN IS-IN G SL R2 R3 Rsense G SL M2 M4 50ohms 50ohms 50ohms M1 M3
M
50ohms
R4
R1
This application use the internal charge pump to provide the high side floating voltage. This voltage can be provided by an external source also.
MC33253
MOTOROLA
rev3.0 - 13/15
MC33253
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol
VCC C2 CP_OUT SRC_HS1 GATE_HS1 /IN_HS1 IN_HS1 /IN_LS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A C1 IS+ ISGND2 GATE_LS2 IN_LS2 /IN_LS2 IN_HS2 /IN_HS2 GATE_HS2 SRC_HS2 /CCS G_EN IS_OUT
Pin Description
Supply1 Charge Pump Capacitor Charge Pump Out Source 1 Output High Side Gate 1 Output High Side Neg. Input High Side 1 Pos. Input High Side 1 Neg. Input Low Side 1 Pos. Input Low Side 1 Gate 1 Output Low Side Power Ground Linear Regulator Output Supply 2 Analog Ground (A.O.P) Charge Pump Capacitor Sense OpAmp Pos. Input Sense OpAmp Neg. Input Logic Ground 2 Gate 2 Output Low Side Pos. Input Low Side 2 Neg. Input Low Side 2 Pos. Input High Side 2 Neg. Input High Side 2 Gate 2 Output High Side Source 2 Output High Side Enable Cross Conduction Suppression Global Enable Sense Current OpAmp Output
MC33253
MOTOROLA
rev3.0 - 14/15
A
28
D
15
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN M
E
H
1 14 PIN 1 IDENT
B
0.25
M
B
L 0.10 C C
SEATING PLANE
e B 0.025
M
MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.13 0.29 B 0.35 0.49 C 0.23 0.32 D 17.80 18.05 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 L 0.41 0.90 0 8
CA
S
B
A1
S
A
CASE 751F-05 ISSUE F
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JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-344-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334
HOME PAGE: http://www.motorola.com/semiconductors
MC33253
MOTOROLA
MC33253/D

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